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integrated silicon solution, inc. www.issi.com 1 rev.? b 12/01/2010 copyright ? 2010 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat- est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is62wv1288dall/dbll is65wv1288dall/dbll ? 128k?x?8? low? voltage, ? ultra ? low? power?cmos? static?ram features ? high-speed access time: 35ns, 45ns, 55ns ? cmos low power operation: 12 mw (typical) operating 4 w (typical) cmos standby ? ttl compatible interface levels ? single power supply: 1.65v--2.2v v dd (62wv1288d all) 2.3v--3.6v v dd (62wv1288dbll) ? fully static operation: no clock or refresh required ? three state outputs ? industrial and automotive temperature support ? lead-free available description the issi is62/65wv1288dall and is62/65wv1288dbll are high-speed, 1m bit static rams organized as 128k words by 8 bits. it is fabricated using issi 's high- performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. when cs1 is high (deselected) or when cs2 is low (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we) controls both writing and reading of the memory. the is62/65wv1288dall and is62/65wv1288dbll are packaged in the jedec standard 32-pin tsop (typei), stsop (typei), sop, and 36-pin mini bga. functional?block? diagram ? december?2010 a0-a16 cs1 oe we 128k x 8 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 cs2
2 integrated silicon solution, inc. www.issi.com rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ? pin?descriptions a0-a16 address inputs cs1 chip enable 1 input cs2 chip enable 2 input oe output enable input we write enable input i/o0-i/o7 input/output nc no connection v dd power gnd ground 36-pin?mini?bga?(b)??(6mm?x?8mm)? 32-pin? tsop?(type?i)?(t), ?? 32-pin?stsop?(type?i)?(h)? pin configuration 32-pin?sop?(q) 1 2 3 4 5 6 a b c d e f g h a0 i/o4 i/o5 gnd v dd i/o6 i/o7 a9 a1 a2 oe a10 cs2 we nc nc cs1 a11 a3 a4 a5 nc a16 a12 a6 a7 a15 a13 a8 i/o0 i/o1 v dd gnd i/o2 i/o3 a14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 we cs2 a15 v dd nc a16 a14 a12 a7 a6 a5 a4 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd v dd a15 cs2 we a13 a8 a9 a11 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3
integrated silicon solution, inc. www.issi.com 3 rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ? absolute?maximum? ratings (1) ? symbol? parameter ? value ? unit ? v term terminal voltage with respect to gnd C0.5 to v dd + 0.5 v v dd v dd relates to gnd C0.3 to 4.0 v t stg storage temperature C65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (1,2) ? symbol? parameter ? conditions? max. ? unit ? c in input capacitance v in = 0v 6 pf c i/o input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. truth ? table ? mode? we? cs1? cs2? oe ? i/o?operation? v dd ?current? ? not selected x h x x high-z i sb 1 , i sb 2 (power-down) x x l x high-z i sb 1 , i sb 2 output disabled h l h h high-z i cc read h l h l d out i cc write l l h x d in i cc
4 integrated silicon solution, inc. www.issi.com rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ? ac ? test? loads figure?1. r1 5 pf including jig and scope r2 output vtm figure?2. ac ? test?conditions ? parameter ? unit? unit? unit? ? ? ? ? (2.3v-3.6v) ? (3.3v?+?5%)? (1.65v-2.2v) ? input pulse level 0.4v to v dd - 0.3v 0.4v to v dd - 0.3v 0.4v to v dd - 0.3v input rise and fall times 1v/ ns 1v/ ns 1v/ ns input and output timing vdd /2 vdd + 0.05 0.9v and reference level (v ref ) 2 output load see figures 1 and 2 see figures 1 and 2 see figures 1 and 2 r1 ( ? ) 317 317 13500 r2 ( ? ) 351 351 10800 v tm (v) 3.3v 3.3v 1.8v r1 30 pf including jig and scope r2 output vtm
integrated silicon solution, inc. www.issi.com 5 rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ? dc?electrical? characteristics? (over operating range) v dd ?=? 2.3v-3.6v ? symbol? parameter ? test ?conditions? min. ? max. ? unit ? v oh output high voltage v dd = min., i oh = C1.0 ma 1.8 v v ol output low voltage v dd = min., i ol = 2.1 ma 0.4 v v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage (1) C0.3 0.8 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , outputs disabled C1 1 a note: 1. v il ( min.) = C0.3v dc; v il (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v ih ( max.) = v dd + 0.3v dc; v ih ( max.) = v dd + 2.0v ac (pulse width < 10 ns). not 100% tested. dc?electrical? characteristics? (over operating range) v dd ?=?3.3v?+?5% ? symbol? parameter ? test ?conditions? min. ? max. ? unit ? v oh output high voltage v dd = min., i oh = C1 ma 2.4 v v ol output low voltage v dd = min., i ol = 2.1 ma 0.4 v v ih input high voltage 2 v dd + 0.3 v v il input low voltage (1) C0.3 0.8 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , outputs disabled C1 1 a note: 1. v il ( min.) = C0.3v dc; v il (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v ih ( max.) = v dd + 0.3v dc; v ih ( max.) = v dd + 2.0v ac (pulse width < 10 ns). not 100% tested. dc?electrical? characteristics (over operating range) v dd =? 1.65v-2.2v ? symbol? parameter ? test ?conditions? v dd ? min. ? max. ? unit ? v oh output high voltage i oh = -0.1 ma 1.65-2.2v 1.4 v v ol output low voltage i ol = 0.1 ma 1.65-2.2v 0.2 v v ih input high voltage 1.65-2.2v 1.4 v dd + 0.2 v v il (1) input low voltage 1.65-2.2v C0.2 0.4 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , outputs disabled C1 1 a note: 1. v il ( min.) = C0.3v dc; v il (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v ih ( max.) = v dd + 0.3v dc; v ih ( max.) = v dd + 2.0v ac (pulse width < 10 ns). not 100% tested.
6 integrated silicon solution, inc. www.issi.com rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ? power ? supply? characteristics (1) ? (over operating range) ? ? -35? -45? -55? ? symbol? parameter ? test ?conditions? ? min. ? max. ? min. ? max. ? min. ? max. ? unit i cc v dd dynamic operating v dd = max., com. 8 6 5 ma supply current i out = 0 ma, f = f max ind. 12 8 7 cs1 = v il auto. 15 12 12 v in v dd C 0.3v, or typ. (2) 4 v in 0.4v i cc 1 operating v dd = max., com. 2.5 2.5 2.5 ma supply current i out = 0 ma, f = 0 ind. 2.5 2.5 2.5 cs1 = v il auto. 3 3 3 v in v dd C 0.3v, or v in 0.4v i sb 2 cmos standby v dd = max., com. 2 2 2 a current (cmos inputs) cs1 v dd C 0.2v, ind. 4 4 4 v in v dd C 0.2v, or auto. 18 18 18 v in 0.2v , f = 0 typ. (2) 0.6 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. operating ?range?(v dd ) ? rang e? ambient? temperature v dd (45 n s ) v dd (35 n s ) ? commercial 0c to +70c 2.3v-3.6v 3.3v +5% industrial C40c to +85c 2.3v-3.6v 3.3v+5% operating ?range?(v dd ) ? ra nge? ambient? temperature v dd s peed ? commercial 0c to +70c 1.65v-2.2v 45ns industrial C40c to +85c 1.65v-2.2v 55ns automotive C40c to +125c 1.65v-2.2v 55ns operating ?range?(v dd ) ? ran ge? ambient? temperature v dd (45 n s ) ? automotive C40c to +125c 2.3v-3.6v
integrated silicon solution, inc. www.issi.com 7 rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ? read?cycle?switching? characteristics (1) ? (over operating range) ? ????????????????? ? ? 35?ns ? ? ? 45?ns ?? ? ? 55?ns ? ? ? symbol? parameter ? min. ? ? max. ? min. ? ? max. ? min. ? ? max. ? ? unit t rc read cycle time 35 45 55 ns t aa address access time 35 45 55 ns t oha output hold time 10 10 10 ns t ac s 1/ t ac s 2 cs1/cs2 access time 35 45 55 ns t doe oe access time 10 20 25 ns t hzoe (2) oe to high-z output 10 15 20 ns t lzoe (2) oe to low-z output 3 5 5 ns t hzcs 1/ t hzcs 2 (2) cs1/cs2 to high-z output 0 10 0 15 0 20 ns t lzcs 1/ t lzcs 2 (2) cs1/cs2 to low-z output 5 10 10 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4 to v dd -0.2v/v dd -0.3v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
8 integrated silicon solution, inc. www.issi.com rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ? ac ? waveforms read?cycle? no. ?1 (1,2)? (address controlled) (cs1 = oe = v il , cs2 = we = v ih ) data valid previous data valid t aa t oha t oha t rc d out address ac ? waveforms read?cycle? no. ?2 (1,3) ( cs1, cs2, oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, cs1= v il . c s2= we =v ih . 3. address is valid prior to or coincident with cs1 low and cs2 high transition. t rc t oha t aa t doe t lzoe t acs1/ t acs2 t lzcs1/ t lzcs2 t hzoe high-z data valid t hzcs address oe cs1 cs2 dout
integrated silicon solution, inc. www.issi.com 9 rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ? write?cycle?switching? characteristics (1,2) (over operating range) ? ????????????????????????? ? ? 35ns ? ? ? 45ns ? ? ? 55?ns ? ? symbol? parameter ? min. ? ? max. ??? min. ? ? max. ? ?? min. ?? max. ? ??? unit t wc write cycle time 35 45 55 ns t scs 1/ t scs 2 cs1/cs2 to write end 25 35 45 ns t aw address setup time to write end 25 35 45 ns t ha address hold from write end 0 0 0 ns t sa address setup time 0 0 0 ns t pwe we pulse width 25 35 40 ns t sd data setup to write end 20 20 25 ns t hd data hold from write end 0 0 0 ns t hzwe (3) we low to high-z output 10 20 20 ns t lzwe (3) we high to low-z output 3 5 5 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4v to v dd -0.2v/v dd -0.3v and output loading specifed in figure 1. 2. the internal write time is defned by the overlap of cs1 low, cs2 high and ub or lb, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. ac ? waveforms write?cycle? no. ?1?(cs1/cs2 controlled, oe = high or low) data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din
10 integrated silicon solution, inc. www.issi.com rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ? ac ? waveforms write?cycle? no. ?2? (we controlled: oe is high during write cycle) write?cycle? no. ?3? (we controlled: oe is low during write cycle) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we dout din data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we dout din
integrated silicon solution, inc. www.issi.com 11 rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ? data ?retention?switching? characteristics ? ? symbol? parameter ? test ?condition? ? min. ? typ. (1) ? max. ? unit v dr v dd for data retention see data retention waveform 1.2 3.6 v i dr data retention current v dd = 1.2v, cs1 v dd C 0.2v com. 0.5 2 a ind. 4 auto. 18 t sdr data retention setup time see data retention waveform 0 ns t rdr recovery time see data retention waveform t rc ns note: 1. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. data ?retention? waveform ?(cs1? controlled) data ?retention? waveform ?(cs2? controlled) v dd cs1 v dd - 0.2v t sdr t rdr v dr cs1 gnd data retention mode v dd cs2 0.2v t sdr t rdr v dr cs2 gnd data retention mode
12 integrated silicon solution, inc. www.issi.com rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ? ordering? information is62wv1288dall ?(1.65v?-?2.2v) industrial? range: ?C40c?to?+85c ? speed?(ns)? order ? part?no. ? package 55 is62wv1288dall-55ti tsop-i is62wv1288dall-55tli tsop-i, lead-free is62wv1288dall-55hi stsop-i is62wv1288dall-55hli stsop-i, lead-free is62wv1288dall-55bi mini bga (6mm x 8mm) is62wv1288dall-55bli mini bga (6mm x 8mm), lead-free ordering? information is62wv1288dbll?(2.3v?-?3.6v) industrial? range: ?C40c?to?+85c 1 ? speed?(ns)? order ? part?no. ? package 45 is62wv1288dbll-45ti tsop-i is62wv1288dbll-45tli tsop-i, lead-free is62wv1288dbll-45hi stsop-i is62wv1288dbll-45hli stsop-i, lead-free is62wv1288dbll-45qi sop is62wv1288dbll-45qli sop, lead-free is62wv1288dbll-45bi mini bga (6mm x 8mm) is62wv1288dbll-45bli mini bga (6mm x 8mm), lead-free automotive ? range: ?C40c?to?+125c ? speed?(ns)? order ? part?no. ? package 45 is65wv1288dbll-45tla3 tsop-i, lead-free is65wv1288dbll-45hla3 stsop-i, lead-free is65wv1288dbll-45qla3 sop, lead-free notes: 1. speed = 35ns for temperature range of 0 o c to +70 o c or for v dd = 3.3v 5%.
integrated silicon solution, inc. www.issi.com 13 rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ?
14 integrated silicon solution, inc. www.issi.com rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ?
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16 integrated silicon solution, inc. www.issi.com rev.? b 12/01/2010 is62wv1288dall/dbll is65wv1288dall/dbll ? note : 1. controlling dimension : mm . 2. reference document : jedec mo-207 08/12/2008 package outline

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